Multiplierless approximation of transforms with adder constraint
Ying‐Jui Chen, S. Oraintara, Trac Duy Tran, K. S. P. Amaratunga, Truong Q. Nguyen · IEEE Signal Processing Letters · 2002
This letter describes an algorithm for systematically finding a multiplierless approximation of transforms by replacing floating-point multipliers with VLSI-friendly binary coefficients of the form k/2/sup n/. Assuming the cost of hardware binary shifters is negligible, the total number of binary adders employed to approximate the transform can be regarded as an index of complexity. Because the new algorithm is more systematic and faster than trial-and-error binary approximations with adder constraint, it is a much more efficient design tool. Furthermore, the algorithm is not limited to a specific transform; various approximations of the discrete cosine transform are presented as examples of its versatility.