Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis
Naofumi Homma, Takahiro Higuchi, Takafumi Aoki · IEE Proceedings - Circuits Devices and Systems · 2002
The paper presents a novel graph-based evolutionary optimisation technique called evolutionary graph generation (EGG) and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. A unique feature of EGG is its capability to handle the general graph structures directly in the evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. The paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called ‘transmigration’, which is to import previously generated good solutions (constant-coefficient multipliers) for creating multipliers with different target coefficients. The authors' observation shows that transmigration accelerates a typical evolutionary run by an average of 8.7 times. This implies that the EGG system can acquire and reuse useful subcircuit structures contained in the previously generated multipliers during the evolution process.