The design of a bit-serial coprocessor to perform multiplication and division on a massively parallel architecture
Robert E. Morley, Gary E. Christensen, T.J. Sullivan, O. Kamin · 2003
The design of a VLSI coprocessor element (COPE) that uses a parallel adder to achieve the increased speed needed by the many multiplications and divisions required by fast Fourier transforms (FFTs), convolutions, and other common operations is discussed. It accepts operands of variable length (N>