APU: specification and design of a multi algorithm ATM policing unit IP
José Antônio Gomes de Lima, Antônio Carlos Cavalcanti, S. Ferreira de Lucena · Symposium on Integrated Circuits and Systems Design · 2002
Today's needs of miniaturization, performance and power consumption of entire connected wireless information processing units and time-to-market constraints, impose design strategies that (re)use building IP (Intellectual Property) blocks with increasing flexibility capabilities. Previous works on ATM layer controller provided designs of chips/cores of multi/single port single ASIC chip [1][2][3][4] and single FPGA chip [5] that implements several algorithm types, for the entire ATM layer processing, by microinstructions programming only. In order to provide designers with less complex (more reusable) IP for that appliance, this paper presents APU: an IP of a hardware core, designed to execute multi algorithm ATM policing functions only.