Greedy algorithm for register-transfer level ALU mapping
Haifeng Zhou, Zhenghui Lin · 2002
We present register-transfer level mapping (RTLM), a library mapping technique for RT level components that supports the current design methodologies using high-level design and design reuse. This technique is well suited for mapping regularly structured datapaths, i.e. ALUs. Experiments show that the RTLM is an effective approach for reuse of datapath components in high-level synthesis.