A high speed metal programmable static RAM compiler for 0.7 mu m CMOS gate array
S. Honnenhalli, J. Shiffer, S. Subramanyam, D. Eastwick, D.Y. Kim, Jianfei Jiang · 2003
A static RAM compiler has been developed for a new 0.7 micron Leff CMOS gate array. The compiler is fully metal programmable and can compile RAMs from 8 bits to 64 K bits with typical access times of 4 ns to 10 ns, respectively. It supports partially decoded RAMs and variable aspect ratios. The compiler is well integrated into CAD tools.>