The analysis and test of real-time performance for time-triggered CAN bus
Liu Jianxin, Guan Xuefeng, Tan Ping · 2008
The time triggered architecture for CAN is analyzed. The implementation issue of time triggered architecture based on PIC16F913 single chip processor and CAN controller MCP2515 is designed. The mathematical model for the CAN bus delay under the worst case is given. And the real-time ability is improved by using the method of TDMA. At last, a test system is build and the result is discussed. The experiment is based on the automotive engine management, the result proves that using time triggered architecture can not only manage the message transmission but also improve the bandwidth utilization.