A Unified Formal Framework for Analyzing Functional and Speed-path Properties
Oswaldo Olivo, Sandip Kumar Ray, Jayanta Bhadra, Vivekananda M. Vedula · 2011
We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in a formal hardware description language providing the semantics of both the functional behavior and timing constraints, and the disciplined use of an SMT solver to analyze speed-path requirements. We are applying our framework for speed-path analysis of several RTL designs from Opencores.