Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level
K. Ara, Kei Suzuki · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005
Maintaining coverage with increasing circuit scale has become a critical problem for logic-verification processes. While transaction-level verification (TLV) is an important step forward, fine-grained (FG) TLV provides better signal-level coverage by reactively changing transactors instead of transaction-level scenarios. Evaluations with a microprocessor design show the effectiveness of FGTLV; all design bugs at the signal level were to be detected, though many were not detected by plain TLV.