Asynchronous FIFO implementation using FPGA
Yanjun Zhang, Chunli Yi, Jinqi Wang, Jinye Zhang · 2011
We introduce a design of asynchronous FIFO on FPGA for the purpose of high-speed, steady data transmission between asynchronous clock domains. In the design, the memory address was organized into one ring list, using gray code as its address code, making uses of double jump technology to finish two asynchronous clock regions between address signals transmission, avoiding the meta-stability well.