Speeding up behavioral test pattern generation using an algorithmic improvement
L. Vandeventer, Jean-François Santucci, Norbert Giambiasi · 2002
In this paper, we focus on an improvement of test pattern generation for circuit descriptions written in hardware description languages according to their behavior. The improvement method stems from the "headlines" defined at the gate level by structural test approaches. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach.>