A word-based RSA crypto-processor with enhanced pipeline performance
Chen-Hsing Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng‐Wen Wu · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
We propose a high speed RSA crypto-processor based on an enhanced word-based Montgomery Multiplication (MM) algorithm. With the help of the proposed Correction Module (CM), the word-based modular multiplier can achieve 100% utilization. A simplified Parity Prediction Module (PPM) is also proposed to eliminate the pipeline stall. Using a 0.18 /spl mu/m CMOS standard cell library, our RSA crypto-processor achieves a 512-bit RSA encryption rate of 375Kbps under 300MHz clock. The result shows that our architecture is cost-effective in terms of area and performance.