Byte and Modulo Addressable Parallel Memory Architecture for Video Coding
Jarno K. Tanskanen, Tero Sihvo, Jarkko T. Niittylahti · IEEE Transactions on Circuits and Systems for Video Technology · 2004
This paper proposes an internal data memory architecture supporting byte and modulo addressing for processors having subword parallel processing capability, or alternatively, multiple SIMD-connected processing elements on-chip. Byte-addressable memory efficiently relieves the data word alignment problem in motion estimation block matching. In addition, a special modulo addressing allows part of the bytes in a word to be accessed simultaneously from the both ends of a circular buffer. With the modulo-addressable memory, the external memory bandwidth can be significantly reduced, while preserving efficient memory access performance in block-matching operations. The proposed data memory architecture consists of parallel memory modules, address computation circuitry, and data permutation network. Designs for different data bus widths (N= 2, 4, 8 bytes) are considered.