An energy-efficient MMAS FFT processor for high-rate WPAN applications
Song-Nien Tang, Jui-Wei Tsai, Tsin‐Yuan Chang · 2011
This paper presents an energy-efficient FFT processor providing high throughput rate for wireless personal area network (WPAN). By using a proposed mixed-memory-access-scheduling (MMAS) scheme in the multipath-delay-feedback (MDF) architecture, energy-efficiency is improved for it provides the same high throughput rate with relatively lower power consumption. A test chip of a 2048-point FFT processor has been designed using UMC 90nm process with a core area of 1.18 mm2excluding the test module. The proposed 2048-point FFT can provide a high throughput rate of 2.4 GS/s at 300 MHz with power consumption of 127 mW by post-layout simulation. Compared to the referred, a saving in power dissipation of 20% or 45% can be achieved at the same throughput rate.