5×4 Gbps 0.35 micron CMOS CRC generator designed with standard cells
Juan María, N. Serrano · 2003
Design highlights for a 32-bit parallel and highly pipelined cyclic redundancy code (CRC) generator are presented. The design can handle 5 different channels at an input rate of 2 Gbps each (the total output throughput is 5/spl times/4 Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35/spl mu/m standard CMOS process using the properties of Galois fields and has been conceived as a "free" IP.