Analysis of a DS-CDMA receiver DLL architecture
J.G.O. Moss, A.M. Street, David J. Edwards, M.J. Mehler · 2002
This paper explores the design of a baseband direct-sequence CDMA system using a delay-locked loop (DLL) for chip synchronisation, for use in a high speed wireless data link. The performance of some feedback loop controllers is analysed, and control aspects of the inherent loop delay due to the integrate and dump action are considered. It was decided that a decision directed DLL (DD-DLL) was simplest to implement for the high chip-rate application, and the synchronisation of a 100 Mchips/second indoor wireless-LAN was simulated using a measured 5 GHz radio channel. Approximate expressions are presented for the theoretical noise performance metrics of jitter and mean time to lose lock (MTLL) for the proposed DLL.