A study of VLSI design for DPCM coding
Naoki Mukawa, Yutaka Suzuki, H. Kuroda, Hiroshi Yoshimura · 2005
This paper describes custom designed VLSI coder and decoder, which transmit time division multiplexed (TDM) color signals at 32 Mbit/sec. Two-dimensional intraframe DPCM prediction, variable word length coding, and data buffer to smooth the data rate are devised on one coder chip. Reverse function are devised on one decoder chip. Test sequence is investigated for logic design purposes. Several techniques, e.g., double phased clock and prediction loop modification are employed to simplify the configuration and to ensure the operation rate of video processing.