A floating point pipeline CORDIC processor with extended operation set
D.E. Metafas, C.E. Goutis · 1991
A novel architecture of a digital signal processing (DSP) floating point, pipelined processor is presented which is based on the CORDIC and CCM algorithms. It provides for the first time a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications, e.g. real-time DSP and matrix equation solving problems.>