Top-1: a snoop-cache-based multiprocessor
Nobuyuki Oba, Atsushi Moriwaki, S. Shimizu · 1990
A novel cache coherence protocol and the performance analysis of a snoop-cache-based multiprocessor, TOP-1, which is tightly coupled and has pure shared memory, are presented. TOP-1 has two 64-b buses with interleaved address access to provide a high data-transfer rate, and a large snoop cache to provide a high cache hit ratio. It also has a TOP-1 hybrid coherence protocol, which allows a write-update protocol and a write-invalidate protocol to exist simultaneously. These protocols can be dynamically changed on the fly without any coherence problem. Each processor card has a statistics unit which collects various important statistical data without any hardware overhead. An overview of the TOP-1 architecture and its concepts is presented. The authors also present the TOP-1 hybrid protocol and explain how it works. They discuss the TOP-1 protocol and its performance by comparing the write-update and write-invalidate protocols.>