Describing controlling hardware in VHDL
J. Spillane, Zainalabedin Navabi · 2002
A description style for synthesizable description of synchronous state machines with asynchronous control is presented. This style uses an implicit clock at an abstraction level convenient for hardware designers. High level behavioral constructs of VHDL including WAIT statements are allowed in this synthesis style. Hardware correspondence for all allowable constructs have been designed and complete examples have been implemented.>