Semiconductor IP core for ultra low power MPEG-4 video decode in system-on-silicon
John A. Dunlop, A. Simpson, S. Masud, Moira Wylie, J. Cochrane, R. Kinkead · 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). · 2003
An ultra low power, hardware accelerated architecture based semiconductor intellectual property core for MPEG-4 has been developed. This encompasses the simple profile of the video decoding algorithm. The core can provide motion picture quality video at up to CIF resolution. The implementation is based on the application of hardware acceleration of compute-intensive operations with an embedded RISC processor acting purely as a host controller. The architecture comprises custom hardware designs for lookup table decoders, bitstream parsing, discrete cosine transforms, motion compensation and colour space conversion. The hardware-software co-design approach results in high efficiency in both area and performance. The design has been validated on an FPGA-based development board with an LCD panel for visual demonstration of real-time decoded streaming video sequences. This MPEG-4 video decoder core has been ported to 130 nm ASIC technology using system-level integration techniques where the power dissipation is around 10 mWatts. The design is ideally suited to high-volume system-on-chip solutions for a wide range of wireless multimedia communication applications.