A fast nonenumerative automatic test pattern generator for path delay faults
Spyros Tragoudas, Dimitrios Karayiannis · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999
This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance.