Switching Activity Based Method for Minimizing Testing Power in Digital Circuits
K. Paramasivam, Kandasamy Gunavathi, Non-members · 2006
Optimization of testing power is a major signiflcant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. In this paper a novel method is proposed to reduce the testing power and total energy by reordering the sequence of test vectors for minimum switching activity of the Circuit Under Test (CUT). Graph theory concept is used to develop the reordering algorithm which is based on heuristic approach to flnd near optimal solution for the problem. Fault coverage of the CUT is not afiected in this algorithm. The reduction of power dissipation and total energy during testing leads to increase in reliability of the circuit. Experimental results of the proposed algorithm with ISCAS85 benchmark circuits show that the switching activity is reduced signiflcantly compared to existing works.