A high-performance full-motion video compression chip set
Peter A. Ruetz, Po Tong, D. Bailey, P. Luthi, Peng Hwa Ang · IEEE Transactions on Circuits and Systems for Video Technology · 1992
A seven-chip set which performs the functions associated with video and image compression algorithms, and CCITT H.261 in particular, has been designed, fabricated, and is fully functional. The major functions performed by the devices include motion estimation, DCT and IDCT, forward and inverse quantization, Huffman coding and decoding, BCH error correction, and loop filtering. The chips that perform the predictive and transform coding section of the algorithm operate with pixel rates up to 40 MHz. Array-based technologies of 1.5 and 1.0 mu m CMOS were used extensively to achieve a 28 man-month design time. Each die is less than 10 mm on a side.>