Design of CMOS circuits for stuck-open fault testability
Anura P. Jayasumana, Yashwant K. Malaiya, Rochit Rajsuman · IEEE Journal of Solid-State Circuits · 1991
A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes.>