Power-/energy-efficient BIST schemes for processor data paths
N. Kranitis, Dimitris Gizopoulos, Antonis Paschalis, Mihalis Psarakis, Y. Zorian · IEEE Design & Test of Computers · 2000
Processor core power is primarily consumed in a data path consisting of high-activity functional modules. We propose low-power/energy BIST schemes for data path architectures built around the most common combinations of multipliers, adders, ALUs, and shifters.