02 2012 64 64 6198433 10.1109/MDT.2012.2196611 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198433 <![CDATA[ 02 2012 72 72 6198434 10.1109/MDT.2012.2196612 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198434 <![CDATA[ 02 2012 79 79 6198435 10.1109/MDT.2012.2196613 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198435 <![CDATA[Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results
Brady Benware, Chris Schuermyer, Manish Sharma, Thomas Herrmann · IEEE Design & Test of Computers · 2012
The yield of an integrated circuit (IC) is well known to be a critical factor in the success of an IC in the market place. Achieving high stable yields helps ensure that the product is profitable and meets quality and reliability objectives. When a new manufacturing process is introduced, or a new product is introduced on a mature manufacturing process, yields will tend to be significantly lower than acceptable. The ability to meet profitability and quality objectives, and perhaps more importantly, time-to-market and time-to-volume objectives depend greatly on the rate at which these low yields can be ramped up. While the yield ramp depends on both the yield learning and yield enhancement cycle times, this work focuses on significantly increasing the value of test data and the yield learning rate.