A channel decoder implemented by CMOS analog circuits in digital communication system
Shuhui Yang, Xuehua Li, Yafei Wang · 2008
To realize low power channel decoder in digital communication system, basing on the a-posteriori probability algorithm, the paper fabricates an analog probability decoder of trellis code by using CMOS analog circuits. The decoding performance is given. When the SNR is over 4.8dB, for 950KHz input signal, the analog decoder’s BER is zero. If the input signal is 6MHz, the BER will be about 10−4.The highest speed of the decoder can be up to 20MHz. Simulation results also show that the analog decoder decreases at least one order of magnitude in power consumption and chip area at the same rate compared with the digital decoder. The design method is also suitable for implementing the analog decoders of Turbo code and LDPC code.