Modeling a reconfigurable system for computing the FFT in place via rewriting-logic
Maurício Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo Pezzuol Jacobi, Reiner W. Hartenstein, De Brasília, Fachbereich Informatik, Universität Kaiserlautern · 2003
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the Fast Fourier Transform – FFT using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions. 1.