A 300-MHz 64-b quad-issue CMOS RISC microprocessor
B.J. Benschneider, Andrew J. Black, William J. Bowhill, Sharon M. Britton, D.E. Dever, D.R. Donchin, R.J. Dupcak, Richard Fromm, M.K. Gowan, P.E. Gronowski, M. Kantrowitz, Marc E. Lamere, Shekhar Mehta, J. Meyer, R.O. Mueller, A. Olesin, R.P. Preston, Donald A. Priore, Sribalan Santhanam, M.J. Smith · IEEE Journal of Solid-State Circuits · 1995
This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm/spl times/18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 /spl mu/m, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency.