An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test
A. Basu, T.C. Wilson, D.K. Banerji, Jayanti C. Majithia · 2005
Minimitataon ofthe total testing time of a chip and the extra overhead involved form two key aspects in design for testability. This paper presents an integrated approach for selecting the test plans with the objective of minimizing the combined testability overhead (area and tame). The results of applicataon of the proposed technique on presynthesized datapaths are presented. Two major considerations involved with the incorporation of Built-in-Self-Test (BIST) are increase in chip area and the total test time. Attempts to reduce the area overhead amount to sharing of the hardware elements. Consequently, the scope of overlapping different tests in time is reduced. Thus, reduction of area overhead and testing time turn out to be conflicting objectives. Several algorithms exist which address the issue of scheduling the tests concurrently to minimize the total testing time [l-21. Kim et al, have addressed the issue of area optimization using the minimal set cover technique [3]. Their approach chooses a minimal set of registers to be converted to BILBO elements. The area optimization, thus obtained, is followed by the determination ofa test schedule using the approach proposed in [l]. This paper presents an integrated approach to the area/time trade-off problem, in the context of BILBO methodology. In this approach, the problem is formulated as an integer linear program (ILP) as well as a graph search problem with a heuristic cost function. The proposed cost function is used in conjunction with the well known A* algorithm [4] to obtain a solution. This heuristic approach yields “near optimal” solutions when applied to a few presynthesized circuits used as test cases. Let tij denote the j-th test plan for functional unit i. We assume that a fixed number, P, of test patterns is applied to each functional unit in the circuit. As shown in [5], the total test time Ti, required by test plan t.;j is given by Tj = Sij + (P - 1) * dij , where Sij is the number of steps in tjj and djj is the delay between two consecutive iterations of the test