An FFT core for DVB-T2 receivers
M. Turrillas, Ainhoa Cortés, Igone Vélez, Juan Francisco Sevillano, Andoni Irizar · 2009
This paper presents the design and implementation of a pipeline radix-25SDF FFT core for DVB-T2 receivers. DVB-T2 operation needs 1K/2K/4K/8K/16K/32K multiple mode FFT processors. The radix-25SDF architecture is a new and more efficient architecture, which has been optimized for implementing a multiple mode core. SNR results for different data and twiddle factor bitwidths are provided. Furthermore, the results of the FFT core implementation in an FPGA are presented.