An LSI architecture for block-matching motion estimation algorithm considering chrominance signal
Eizaburo Iwata, T. Yamazaki · 2002
We propose a new LSI architecture of motion estimation based on the full search algorithm of the block-matching method. The LSI architecture proposed has a 1-dimensional systolic array architecture with a pipelined adder which computes the error function in the whole array of circuit. This architecture can be extended to incorporate chrominance components processing. This method has a significant improvement of the motion estimation performance compared to the conventional method which regards only luminance pixels, especially on a large search range.