Three bits per cell floating gate NAND flash memory technology for 30nm and beyond
Honami Nitta, T. Kamigaichi, Fumitaka ARAI, Takuya Futatsuyama, Masamori Endo, N. Nishihara, Takaaki Murata, H. Takekida, T. Izumi, Ken‐ichi Uchida, Toru Maruyama, I. Kawabata, Yoshihiro Suyama, Akira Sato, Kazuki Ueno, H. Takeshita, Y. Joko, Shunsuke Watanabe, Y. Liu, H. Meguro · 2009
Three bits per cell NAND Flash Memory Technology for 30 nm and beyond has been successfully developed with floating gate technology. Tight natural Vthdistribution, wide program/erase window, and good cell reliability such as program disturb, endurance and data retention are obtained. 8 level Vthdistributions are successfully demonstrated.