Design and FPGA implementation of systolic FIR filters using the Fermat number ALU
H. Safiri, Mohammad Mahdi Ahmadi, GRAHAM A. JULLIEN, Vassil S. Dimitrov · 2002
This paper addresses the implementation of systolic FIR filters over finite polynomial rings, using FPGAs. The use of residue computations is a potentially beneficial solution to the design of high throughput DSP systems on FPGAs. This paper describes a new architecture for a multiplylaccumulate architecture over the fields GF(I7) and GF(2.57). The computaiional unit containing both GF(l7) and GF(2.57) elements is referred to as the Fermat ALU, The MU is pipelined completely by using abundant number of Flip Flops available in Xilinx FPGA parts. The simulation results show a relatively high throughput for the filter designed using this methodology.