A floating point rectangular systolic array on a chip
R.J. Clarke, I.A. Curtis, AP Clarke, Warren Marwood · 2003
The logical design and architecture of a floating point systolic array on a chip are described. The layout is presented, with a microphotograph of a functional chip fabricated in a 1 mu m CMOS process. The instruction set of the chip is described, and its application to matrix operations is discussed. The chip will function either in isolation or in a cascaded one- or two-dimensional array. In these latter configurations it will be possible to build processing nodes with computing rates in excess of 1 Gflops.>