Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer
Tomoyasu Hasegawa, Y. Homma, Michitaka Kameyama · 2005
A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.