A High-Performance Second-Generation Sparc Mcm
David B. Tuckerman, D. Benson, H. Moore, J.G. Horner, Jeremy Gibbons · 2005
ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.