Testing the configurability of dynamic FPGAs
N. Park, Sameer Jagadish Ruiwale, Fabrizio Lombardi · 2002
This paper addresses configurability testing of dynamic FPGAs, i.e. the process to test the state configuration of the FPGA through specific functions which permits one to establish controllability and observability (by read and write operations). Configurability is accomplished in a dynamic FPGA by using a dedicated CPU interface. The CPU interface is characterized by different functional modules (mainly at register level) to permit state access; this is achieved using mapping, masking and addressing functions, and is tested for stuck-at and bridging faults in the bits of the Map and Mask Registers. The proposed approach for configurability testing has been evaluated on the XC6216 FPGA.