Memory controller design in VLSI
N. Schumacher · 2003
The author presents an overview of the 370 microprocessor chip set, which consists of the processing unit, floating-point, bus-to-bus adapter, cache controller, and memory controller chips. The memory controller is described in detail. The existing CMOS 1- mu m technology and design system are illustrated from logic input up to mask data generation. Logic simulation aspects are described in a way suitable for designers. The primary tasks of a memory controller are shown, subdivided into controller-controlled functions (refresh, error detection and correction, address checking, scrib), additional features (diagnostics, speed control, debug facilities, self-test on chip), and system-controlled functions, (memory accesses, message commands). Performance data of the realized memory controller and its floorplan are given. Costs and turnaround times are discussed.>