A flexible hardware encoder for systematic low-density parity-check codes
Hemesh Yasotharan, Anthony Chan Carusone · 2009
This paper proposes a flexible low density parity check encoder. This encoder simplifies the calculations found in other flexible encoders by increasing memory usage, allowing for parallelization and faster encoding. The flexibility of this encoder allows it to be used in emerging multi code applications and standards. To evaluate the encoder, a Verilog description was developed and synthesized on an Altera Stratix platform for the IEEE 802.16e WiMAX standard. The implementation used 11,430 logic elements and operated at a maximum clock frequency of 60 MHz. The throughput ranged from 119 Mbps for rate-1/2 codes to 357 Mbps for rate -5/6 codes. A speedup of 2.5-6 times is demonstrated compared to the prior art.