A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
Yanni Chen, D.E. Hocevar · 2004
This paper presents an implementation of irregular low density parity check decoder using both FPGA and ASIC. The considered low density parity check code has code rate 1/2, codeword length of 8088 bits and parallel factor of 24. The partly parallel structure, memory management, message alignment and addressing generation schemes needed to realize the underlying graph connectivity will be discussed. With the target FPGA device Xilinx XC2V8000 and maximum number of 25 iterations, the information decoding throughput could achieve up to 40 Mbps. By using the same configuration and Texas Instruments' GS-40 0.11 /spl mu/m ASIC process technology, decoder data rate of 188 Mbps could be achieved for this decoder.