Compiler-directed instruction cache leakage optimization
Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut Kandemir, N. Vijaykrishnan, M.J. Irwin · 2002
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor 's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.