Implementation of Double Precision Floating Point Multiplier on FPGA
A. Keerthi, K.V .Koteswararao · International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering · 2014
Multiplication is one of the common arithmetic operations in Digital Signal Processing(DSP) computations.The proposed design is an implementation of an IEEE-754 Double Precision Floating Point Multiplier, which is better when compared to a single precision multiplier[1] because of its wider dynamic ranges and accuracy.A Double Precision Multiplier is designed using Xilinx 12.4 ISE tool and the design verification was done on Xilinx Vertex-4 ML403 platform which handles overflow, underflow cases and Truncation mode.A Comprehensive simulation and analysis of multiplier output is done using Xilinx ISim simulator and a test bench is written to generate an input stimulus.