High performance single chip dataflow processor
G. Kuru · 2002
A new dataflow concept, Multiple Input Node, is introduced to overcome the performance and efficiency degradation problems that exist in the current dataflow computation models. Multiple Input Node is a new computation node which has 4 inputs, hence it can accept up to 4 token packets at a time. The unique architecture of the Multiple Input Node reduces the number of token packets in the system and therefore increases performance. Also introduced is a newly designed dataflow processor architecture, Multiple Input Node Dataflow Processor, which utilizes the Multiple Input Node concept. The processor also has RISC based design, 4 stage pipeline architecture, peak performance of 120 MIPS, and a direct matching scheme. The architecture has been realized as a single chip ASIC by using European Silicon Structures 0.7 micron CMOS standard cell process.