Surprises in sequential redundancy identification
Mahesh A. Iyer, David E. Long, M. Abramovici · 1996
This paper addresses some misconceptions about redundancy in synchronous sequential circuits. We provide examples to illustrate the differences between untestability and redundancy and discuss existing techniques to identify sequential redundancy. We show that some of these methods are based on incorrect theoretical results. Specifically, we show that untestable faults in balanced pipeline circuits are not necessarily redundant, and that a constant function (i.e. a signal that is always 0 or 1 after initialization) does not always indicate a redundancy. We also show that adding a global reset mechanism or retiming synchronous circuitry may introduce redundancies. 1. Introduction Unintentional logical redundancies may be introduced in a circuit without the knowledge of the designer. Identifying these redundancies may provide useful feedback for designers, helping them in locating design errors or finding ways to simplify the circuit. Redundancy identification (RID) ca...