Signal integrity fault analysis using reduced-order modeling
Amir Attarha, Mehrdad Nourani · Proceedings - ACM IEEE Design Automation Conference · 2002
This paper aims at analysis of signal integrity for the purpose of testing high speed interconnects. This requires taking into account the effect of inputs as well as parasitic RLC elements of the interconnect. To improve the analysis/simulation time in integrity fault testing, we use reduced-order modeling that essentially performs the analysis in the frequency domain. To demonstrate the generality and usefulness of our method, we also discuss its application for test pattern generation targeting signal integrity loss.