A binary block matching architecture with reduced power consumption and silicon area requirement
Marcelo Mikiyo Mizuki, Usha Desai, I. Masaki, Anantha P. Chandrakasan · 2002
Motion estimation is essential for reducing bit rate by exploiting the temporal redundancy existent in image sequences. MPEG, one of the current standards for video coding, specifies the use of block matching (BM) for motion estimation. Conventional block matching is based on the mean-absolute difference (MAD) distortion metric, which requires a large number of 8-bit arithmetic computations and thereby limits wider usage. This paper examines the possibility of using a binary distortion metric based on contour data to reduce the silicon area and power consumption of the block matching chip by a factor of 5 or more. Our simulation results indicate that the performance of the proposed binary system for a restricted class of sequences, such as "head-and-shoulder" images, is very close to that of conventional gray level methods. Detailed design of the binary block matching (BBM) chip is currently underway. Potential applications include low power, portable video devices and machine vision applications such as stereo matching and template matching.