Designing the Low-Power MCORE TM Architecture
Jeff Scott, Lea Hwang Lee, John Arends, Bill Moyer · 1998
The MCORE microRISC architecture has been developed to address the growing need for long battery life among today's por- table applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the Instruction Set Architecture (ISA), the custom datapath design, and the clocking methodology . Finally, we will discuss two system solutions utiliz- ing the MCORE processor, presenting power, area, and perfor- mance metrics.