Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources
Salvador Manich, Lucas Garcia-Deiros, Joan Figueras · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007
Test-pattern generators (TPGs), based on arithmetic operations, are becoming cost-effective built-in self-test solutions for circuits with embedded processors. Similar to pseudorandom TPGs, arithmetic TPGs use reseeding to reach high levels of fault coverage (FC). In this paper, we propose a method of searching for an effective reseeding strategy, guaranteeing a specified FC level. The proposed methodology minimizes the total test time under the constraint of the total memory resource allocated to store the seeds. The minimization is performed by a binary search that speeds up the seed selection. Experiments with benchmark circuits have shown an average reduction of 43.47% in test time compared with the three previous methodologies.